Open Access Open Access  Restricted Access Subscription or Fee Access

Ternary Logic Design Approach - From CMOS to CNTFET

Suman Rani, Gagandeep Kaur, Balwinder Singh Lakha


The goal of this review is to offer a broad study on the ternary logic designs based on CMOS (complementary metal-oxide-semiconductor) and CNTFET (carbon nanotube field effect transistor) suitable for energy efficient and high-performance VLSI design. Performance investigation of the ternary logic-based designs will be the primary emphasis as the ternary logic is a good substitute for the conventional binary logic among all the multiple-valued logics because it permits simple and power efficient digital design owing to the lessen chip area and circuit overhead due to interconnects. The usefulness of this paper lies in the field of academic and research related to low power and high-speed VLSI design, and nano-scale devices. A brief summary of ternary logic designs based on CMOS and CNTFET is presented. This study enables the reader to clear basic concepts about the ternary logic designs and their performance analysis.

Keywords: CMOS, carbon nanotube field effect transistor (CNTFET), multi-valued logic (MVL) design, ternary logic, HSPICE

Full Text:



Ray HB, Anvar AZ, and Walt ADH. Carbon Nanotubes-the route toward applications. Science. 2002; 297(5582): 787-792 p.

International Technology Roadmap for Semiconductors (ITRS), Emerging Research Device Summary, 2015

Singh A, Khosla M, Raj B. Comparative Analysis of Carbon Nanotube Field Effect Transistors.Proc. of GCCE; 2015

Chowdhury AH, Akhter N, and Faisal AA. Performance Analysis and Development of Self- Consistent Model of Carbon Nanotube Field Effect Transistor (CNTFET). Proc. of the Global Engg, Sci. and Tech. conf.; 2012: 28-29p

Moaiyeri MH, Mirzaee RF, Navi. K et al. Efficient CNTFET-based Ternary Full Adder Cells for Nano-electronics, Nano-Micro Lett. 2011; 3(1): 43-50p.

McEuen PL, Fuhrer M and Park H. Single-walled carbon nanotube electronics. IEEE Trans. on Nanotech. 2002; 99(1): 78-85p.

Mukaidono M. Regular ternary logic functions—Ternary logic functions suitable for treating ambiguity. IEEE Trans. Comp.1982; C-35(2): 179–183p.

Lukasiewicz J, logic trójwartościowej O (in Polish), Ruch filozoficzny 5:170–171.English translation: On three-valued logic, in: L. Borkowski (Ed.), Selected works by Jan Łukasiewicz, Amsterdam, North–

Holland:1970, pp. 87–88. Available from: Net Library.

Kleene SC. Introduction to Metamathematics, Amsterdam, The Netherlands: North-Holland: 1952, 332–

p. Available from: Net Library.

Azhari R, Shahhoseini A, Aghaei-liavali F. Stability Improvement and consumption power of CNTFET-

based ternary memory cell, published in IEEE Int Conf. on Res. in Comp. Int. and Comm. Networks:

Moaiyeri MH, A. Doostaregan, Navi K. Design of energy-efficient and robust ternary circuits for

nanotechnology, IET Cir., Dev. Sys.2010; 5 (4): 285–296p.

Balla PC and Antoniou A. Low power dissipation MOS ternary logic family. IEEE J of Solid-St

Cir.: 1984; 19(5): 739–749p.

Heung A and Mouftah HT. Depletion/enhancement CMOS for a lower power family of three-valued

logic circuits. IEEE J of Solid-St Cir: 1985; 20 (2): 609–616p.

Sharifi F, Panahi A, Moaiyeri MH, Sharifi H, Navi K. High-Performance CNFET-based Ternary Full Adders. IETE J of Res. 2017; 1-7p.

Tabrizchi S, Azimi N, and Navi K. Design a novel ternary half adder and multiplier based on carbon nano

tube field effect transistors (CNTFETs). Front of IT & Elect Engg: 2017; 18(3): 423-433p.

Vudadha C, Rajagopalan S, Dusi A, Phaneendra PS, and Srinivas MB. Encoder based optimization of

CNFET based ternary logic circuits. IEEE Trans. on Nanotech 2018;17(2): 299-310p.

Lin S, Kim YB and Lombardi F. CNTFET-Based Design of Ternary Logic Gates and Arithmetic

Circuits. IEEE Trans. on Nanotech. 2011; 10(2): 217-225p.

Samadi H, Shahhoseini A, Aghaei-liavali F. A new method on designing and simulating CNTFET based

ternary gates and arithmetic circuits. Microelectronics Journal. 2017; 63: 41– 48p.

Moaiyeri MH, Nasiri M, Khastoo N. An efficient ternary serial adder based on carbon nanotube FETs.

Eng. Sci. and Tech an int. J. 2016; 19(1): 271-278p.

Moaiyeri MH, Mirzaee RF, Doostaregan A, Navi K, Hashemipour O. A universal method for designing

low-power carbon nanotube FET-based multiple-valued logic circuits. IET Comp Dig Tech. 2013;

(4): 167–181p.

Bacon R. Growth, structure and properties of graphite whiskers. J. App. Phy. 31(2); 1960: 283-290p.

Singh A, Khosla M, Raj B. Circuit compatible model for Electrostatic doped Schottky Barrier

CNTFET. J. Elect. Mat.: 2016; 45(10): 5381–5390p.

Lin S, Kim Y B, and Lombardi F, “Design of a Ternary Memory Cell Using CNTFETs” IEEE

Trans. on Nanotech: 2012; 11(5): 1019-1025p.

Łukasiewicz J. O Logice trójwartościowej. Ruch Filozoficzny: 1920; 5: 170–171p.

Paugh A. Application of binary devices and Boolean algebra to the realization of 3-valued logic circuits.

Proc. of the Inst. of Elect. Engineers. 1967; 114(3): 335 – 338p.

Porat D I. Three-valued digital systems. Proc. of the Inst. of Elect. Engineers.1969;116(6): 947 – 954p.

Mouftah H T , Jordan I B. Implementation of 3-valued logic with c.o.s.m.o.s. integrated circuits.

Electronics Letters.1974; 10(21): 441-442p.

Huertas JL ,Acha JI ,Carmona JI. Implementation of some ternary operators with c.m.o.s. integrated circuits. Elec. Lets. 1976; 12(15): 385 – 386p.

Mouftah HT, Jordan IB. Design of Ternary COS/MOS Memory and Sequential Circuits. IEEE

Trans. 1977; C-26(3): 281 – 288p.

Etiemble D and Israel M. Implementation of Ternary Circuits with Binary Integrated Circuits. IEEE

Trans. on Comp. 1977; C-26(12): 1222 – 1233p.

Mouftah HT, Smith KC. Design and implementation of three-valued logic systems with M.O.S.

integrated circuits. IEE Proc. G – Elect. Cir. and Sys. 1980; 127(4) :165 –168p.

Mouftah HT , Smith KC. Injected voltage low-power CMOS for 3-valued logic,” IEE Proc. 1982;

(6): 270-271p.

Mouftah HT, and Garba AL. VLSI implementation of a 5-trit full adder. IEE Proceedings. 1984; 131(5):


Ramkumar K, and Nagaraj K. A Ternary Schmitt Trigger,” IEEE Trans. on Circ and Sys.1985; 32(7):


Prosser F, Wu X, and Chen X. CMOS ternary flip-flops and their applications. IEE Proc. E-Comp. and

Dig. Tech.1988; 135(5); 266 – 272p.

Wu XW, and Prof. Prosser FP. CMOS ternary logic circuits. IEE Proceedings. 1990; 137(1): 21-27p.

Zhuang N, and Wu H. Novel Ternary JKL Flip-Flop. Elec. Lett. 1990; 26(15): 1145-1146p.

Mateo D, and Rubio A. Design and Implementation of a 5× 5 trits Multiplier in a Quasi-Adiabatic

Ternary CMOS Logic. IEEE J of Solid-St. Cir. 1998; 33(7): 1111-1116p.

Shou X, Kalantari N, and Green MM. Design of CMOS Ternary Latches. IEEE Trans. On

Cir. and Sys. —I: Regular Papers. 2006; 53(12): 2588-2594p.

Raychowdhury, and Roy K. Carbon-Nanotube-Based Voltage-Mode Multiple- Valued Logic Design.

IEEE Trans. on Nanotech. 2005; 4(2), 168-179p.

Sridharan K, Gurindagunta S, and Pudi V. Efficient Multiternary Digit Adder Design in CNTFET

Technology. IEEE Trnas. on Nanotech.2013; 12(3): 283-287p.

Keshavarzian,P, and Sarikhani R. A Novel CNTFET-based Ternary Full Adder. Circ. Sys, Sig Process.

; 33: 665–679p.

Shin S , Jang E, Jeong JW , Park BG, and Kim KR. Compact Design of Low Power Standard

Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology,” IEEE

Trans. on Elect. Dev. 2015; 62(8): 2396-2403p.

Murotiya SL, and Gupta A. Hardware efficient low power 2-bit Ternary ALU design in CNTFET

Technology. Int. J of Elect. 2016; 103(5): 913-927p.

Kang Y, Kim J, Kim S, Shin S, Jang ES, Jeong JW, Kim KR, and Kang S. A Novel Ternary Multiplier

based on Ternary CMOS Compact Model. Int. Symp. on MVL. 2017, 25-30p.

Srinivasu B, and Sridharan K. Low-Complexity Multiternary Digit Multiplier Design in CNTFET

Technology. IEEE Trans. on Cir. and Sys. 2016; 63(8): 753-757p.

Jafarzadehpour F,and Keshavarzian P. Low-power consumption ternary full adder based on CNTFET.

IET Cir, Dev & Sys. 2016; 10(5): 365-374p.

Sahoo SK, Akhilesh G, Sahoo R, and Muglikar M. High-Performance Ternary Adder Using CNTFET.

IEEE Trans. on Nanotech.2017; 16(3), 368-374p.

Srinivasu B, and Sridharan K. Carbon nanotube FET-based low-delay and low-power multi-digit adder

Designs. IET Cir., Dev & Sys. 2017; 11(4): 352-364p.

Tabrizchi S, Panahi A, Sharifi F, Navi K, and Bagherzadeh N. Method for designing ternary adder cells based on CNFETs. IET Cir.Dev. & Sys. 2017; 11(5): 465-470p.


  • There are currently no refbacks.