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Electrical Performance of the Silicon Nanowire Double Gate FET

Dayal C. Sati, Manoj Kumar, Vivek Kumar, Nripender .


Silicon nanowire (SiNW) metal-oxide-semiconductor field-effect transistor (MOSFET) is a promising candidate of future CMOS device for further scaling. As the cross-sectional dimensions of SiNW channel is very small, cross-sectional shapes should affect electrical characteristics of SiNW FETs. In this work, effects of cross-sectional shapes of gate stack formation on (i) properties of double gate of SiNW FET; (ii) carrier transport properties including on-current, effective carrier mobility and inversion charge density; (iii) electrostatic controllability are investigated. A novel device structure, semi gate-around structure is proposed in this work, which is similar to double-gate structure. Silicon nitride sidewalls are filled at the pedestal of the double-gate structure, which reduces steepness of three-dimensional structure. Therefore, over-etching step time during gate patterning process is reduced. To establish design guideline of cross-sectional shapes of SiNW FET to achieve high on-current (ION), SiNW FETs with various cross-sectional shapes are designed and characterized. Among rectangular, half-circular, tear-like, and tall rectangular cross-sections, SiNW FET with rectangular cross-section exhibits highest on-current for nFET at the channel height of 12 nm and width of 19nm. For analysis of transport properties, effective carrier mobility (eff) and inversion charge density (Qinv) are evaluated. Qinv of rectangular cross-section is increased because of high-density inversion carrier regions around corners compared with planar SOI nFET.


Carbon nanotube, carbon nanotube field effect transistor, silicon nanowire, HSPICE.

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Iwai, H., 1999. CMOS technology-year 2010 and beyond. IEEE Journal of Solid-State Circuits, 34(3), pp. 357–366.

Chern, J.G., Chang, P., Motta, R.F. and Godinho, N., 1980. A new method to determine MOSFET channel length. IEEE Electron Device Letters, 1(9), pp.170–173.

Cui, Y., Duan, X., Hu, J. and Lieber, C.M., 2000. Doping and electrical transport in silicon nanowires. The Journal of Physical Chemistry B. 104(22), pp. 5213–5216.

Cui, Y., Zhong, Z., Wang, D., Wang, W.U. and Lieber, C.M., 2003. High performance silicon nanowire field effect transistors. Nano letters, 3(2), pp.149–152.

Su, L.T., Sherony, M.J., Hu, H., Chung, J.E. and Antoniadis, D.A., 1994. Optimization of series resistance in sub-0.2 μm SOI MOSFET's. IEEE Electron Device Letters. 15(5), pp. 145–147.

Liu, Y., Gluschenkov, O., Li, J., Madan, A., Ozcan, A., Kim, B., Dyer, T., Chakravarti, A., Chan, K., Lavoie, C. and Popova, I., 2007, June. Strained Si channel MOSFETs with embedded silicon carbon formed by solid phase epitaxy. In 2007 IEEE Symposium on VLSI Technology. pp. 44–45.

Kamiyama, S., Kurosawa, E., Abe, S., Kitajima, M., Aminaka, T., Aoyama, T., Ikeda, K. and Ohji, Y., 2009, December. V th fluctuation suppression and high performance of HfSiON/metal gate stacks by controlling capping-Y2 O3 layers for 22nm bulk devices. In 2009 IEEE International Electron Devices Meeting (IEDM). pp. 1–4.

Packan, P., Akbar, S., Armstrong, M., Bergstrom, D., Brazier, M., Deshpande, H., Dev, K., Ding, G., Ghani, T., Golonzka, O. and Han, W., 2009, December. High performance 32nm logic technology featuring 2nd generation high-k+ metal gate transistors. In 2009 IEEE international electron devices meeting (IEDM). pp. 1–4.

Jiang, Y., Liow, T.Y., Singh, N., Tan, L.H., Lo, G.Q., Chan, D.S.H. and Kwong, D.L., 2008, June. Performance breakthrough in 8 nm gate length gate-all-around nanowire transistors using metallic nanowire contacts. In 2008 Symposium on VLSI Technology. pp. 34–35.

Wong, H.S., Tan, L.H., Chan, L., Lo, G.Q., Samudra, G. and Yeo, Y.C., 2009, June. Gate-all-around quantum-wire field-effect transistor with dopant segregation at metal-semiconductor-metal heterostructure. In 2009 Symposium on VLSI Technology. pp. 92–93.

Bangsaruntip, S., Cohen, G.M., Majumdar, A., Zhang, Y., Engelmann, S.U., Fuller, N.C.M., Gignac, L.M., Mittal, S., Newbury, J.S., Guillorn, M. and Barwicz, T., 2009, December. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling. In 2009 IEEE International Electron Devices Meeting (IEDM). pp. 1–4.


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