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Design of Ultra-Low-Power Robust SRAM Cell

Paritosh Sharma, Yogendra Kumar Upadhyay, Kshetra Singh


SRAM is designed to provide an interface with CPU and to replace DRAMs in systems that require very low power consumption. Low power SRAM design is crucial since it takes a large fraction of total power and die area in high-performance processors. An SRAM cell must meet the requirements for the operation in submicron/nano ranges. The scaling of CMOS technology has significant impacts on SRAM cell random fluctuation of electrical characteristics and substantial leakage current. The random fluctuation of electrical property causes the SRAM cell to have a huge mismatch in transistor threshold voltage. Consequently, the static noise margin (Read Margin) and the write margin are degraded dramatically. The SRAM cell tends to be unstable and the low power supply operation becomes hard to achieve. The proposed SRAM cells achieve low power memory operation. This paper presents 45% of power savings compared to other designs.


SRAM, CMOS, Mentor Graphics

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